1. Field of the Invention
The present invention relates to fabrication of a semiconductor device, and more particularly to a method for making a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof.
2. Description of the Prior Art
To improve operation characteristics of a semiconductor device, several types of hetero-junction bipolar transistors have been actively developed. Typical one of them has a SiGe base which is substituted for a silicon base, and utilizes characteristics of narrowing in energy band gap and grading dependently upon Ge content of the SiGe base.
Similarly to a conventional homo-junction transistor, such a hetero-junction bipolar transistor uses a polysilicon as a component material constituting an extrinsic base and an emitter electrode in addition of an impurity diffusing source of the emitter electrode, and a SiGe material as a component material constituting an intrinsic base, thereby allowing an emitter injection efficiency to be increased. Also, in the bipolar transistor, because the intrinsic base is composed of an ultra-thin layer doped with an impurity of high concentration, a current gain and a switching speed thereof can be improved.
As integration of a semiconductor device is improved higher, i.e. as a semiconductor device is scaled down in size, a selective epitaxy growth is developed to form an epitaxial thin film and also it has been actively researched that a metallic silicide film, for example a TiSi.sub.2 film, in place of a polysilicon film is used as a thin film for base electrode.
FIG. 1 shows the construction of a prior art n-p-n type hetero-junction bipolar transistor in which a SiGe intrinsic base is fabricated by a super self-aligned and selective epitaxy grown.
Fabrication of the bipolar transistor will be briefly described below with reference to FIG. 1.
First, after sequential formation of an n.sup.+ subcollector 2 and an n.sup.- collector 3 on a silicon substrate 1, a trench isolation is performed to form a trench and then an insulating material is filled into the trench to form an isolation insulating layer 4.
Next, a patterned insulating layer 5, a p.sup.+ polysilicon layer 6, an insulating layer 7 and a side nitride layer 8 are sequentially formed thereon to define an n type collector region 9, and then an impurity is selectively implanted into the n type collector region 9. The p.sup.+ polysilicon layer 6 is provided to serve as a base electrode thin film.
Subsequently, on a defined active region, an intrinsic SiGe base 10 is formed by a gas source MBE (molecular beam epitaxy), and a polysilicon layer 11 is formed by a selective epitaxy grown. The polysilicon layer 11 is provided to electrically connect the p.sup.+ polysilicon layer 6 with the SiGe base 10. Thus, a region occurring a parasitic capacitance between the collector and the base is restricted only by the polysilicon layer 11.
Finally, after formation of a side wall insulating layer 12 at the intrinsic SiGe base, an emitter 13 is formed in self-alignment and electrodes 15 are formed by metallization. As a result, the hetero-junction bipolar transistor of FIG. 1 is fabricated.
As described in the above-mentioned prior art method, the intrinsic base 10 is composed of a SiGe material, thereby allowing an emitter injection efficiency to be increased. Additionally, the collector and the base are self-aligned and the emitter and the base also are self-aligned.
Furthermore, because a parasitic capacitance occurring region is limited to a pattern region constituted by the side nitride layer 8 and the side wall insulating layer 12, a parasitic resistance of the base can be reduced by adjustment of the thickness of the pattern region.
However, since the parasitic capacitance region between the collector and the base is defined by a pattern of the polysilicon layer 11 using a lateral wet-etching, stability of the definition process is lowered in the uniformity aspect or the reproduction aspect, so that such a bipolar transistor may be degraded in performance.
In the prior art method, also, since a selective epitaxy grown, which is extremely slowly carried out, is utilized two times in order to form the base 10 and the polysilicon layer 11 and component materials of the base and polysilicon layer are different from each other, the fabrication sequence is complicated and a yield of production is seriously lowered.
In addition, if a polysilicon is grown even only a very little on the ultra-thin base 10, the bipolar transistor suffers a seriously bad influence, so that it may be mal-operated.